kicad-developers team mailing list archive

[Ouabache Designworks <z3qmtr45@xxxxxxxxx>]

On Thu, Mar 8, 2018 at 8:26 AM, Andy Peters <devel@xxxxxxxxx> wrote:

>
> > On Mar 7, 2018, at 9:22 PM, Ouabache Designworks <z3qmtr45@xxxxxxxxx>
> wrote:
> >
> >
> > If you are doing a PCB with a FPGA on it then you really want that FPGA
> designer to be using kicad to design their padring. Kicad could fill this
> niche and it would make your job a lot easier.
>
> If only it was that simple. FPGA (and to some extent, microcontroller) pin
> swapping during layout is a holy grail. The problem is that it’s not as
> simple as it seems. The layout person cannot arbitrarily assign pinouts
> without understanding the specific chip I/O architecture and rules and also
> understanding the FPGA design. Our layout guy is literally on the other
> side of a low wall from me, and I hear his cursing about pin selection all
> the time!
>
>
Andy,

All of these are good points and they fall into what I call "Engineering
notes". A schematic alone is not enough information to layout a PCB. The
design engineer must also include a long list of engineering requirements
that must be meet in order for the board to actually
work. Most of these involve Signal Integrity ,EMI,ESD,Power and timing.

Kicad need to develop a language so that the design engineer can enter
these notes in a machine readable format that is passed to the Layout
programs DRC tests.



An obvious house rule is one we have at the day job: before a PCB is
> released, the FPGA tools are run on the design to ensure that you don’t get
> timing screw-ups and you don’t have illegal pin locations. The problem, of
> course, is that you need to have enough of the FPGA design done before you
> can do that, and there’s always someone with a schedule demanding that the
> board be sent out for fab before you’ve even started simulating your design.
>
>
This is opposite of the problem that we have with ASICs. The ASIC usually
leads the board development by at least one year so you might have to
design the padring before the board design team has even been staffed. This
is why you want your IC designers to be
able to do a partial design with only the major chips to find obvious
problems.

You could create a fpga design with no logic but the correct I/O pads that
toggled at the correct rates. That would let you test out your board before
the real design was ready and could even do your JTAG board testing.

John Eaton