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Re: Bus upgrades merge


Rebased my branch (like I mentioned before, JP's usability concerns have
been addressed for the moment by disabling immediate update until I can
come up with a better long-term fix)

On Sat, Mar 30, 2019 at 1:07 PM jp charras <jp.charras@xxxxxxxxxx> wrote:

> Le 30/03/2019 à 13:33, Wayne Stambaugh a écrit :
> > Jon,
> >
> > I wanted to test complex hierarchy bus net connections which I just
> > haven't had time to look at.  JP, did you check this during your
> > testing?  If so and you didn't find any issues, then I will merge this
> > as soon as I get a chance.  If not, then I would like to test this and
> > make sure there are no issues before we merge it.
> >
> > Cheers,
> >
> > Wayne
> Yes I tested it with a few large projects an a large and complex (4
> sheets using the same file) hierarchy (but only one sample)
> I already sent to Jon this test project (unfortunately not free).
> I did not see issues with the latest code.
> However I found a usability issue (noticeable with large projects):
> I am guessing the netlist is updated after each schematic change.
> On my computer (not a slow computer) for large designs this update after
> each change takes 1 to 2 seconds on W7 32bits.
> This is a bit annoying.
> But the actual issue is the fact there are too many useless updates,
> especially before a symbol is actually added to the schematic:
> When I tray to add a new symbol (from the Place symbol tool or from the
> hotkey "C") it looks like there is an update when the symbol is loaded
> (but not yet placed) and during placement each time the symbol is
> modifed (rotated, mirrored, converted...).
> I also see this delay when entering or leaving a hierarchical sheet.
> For large designs, this could be blocking.
> Perhaps the immediate update could be disabled (option?) for large designs.
> (Jon already knows that)
> --
> Jean-Pierre CHARRAS

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